Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications. (November 2018)

• Record Type: Journal Article
• Authors: Adenekan, Olujide; Holland, Paul; Kalna, Karol
• Is Part Of: Microelectronics journal. Volume 81(2018)
• Page Start: 94
• Page End: 100
• Publication Date: 2018-11
• Subjects: Super-junction (SJ) -- Multi-gate (MG) -- Power MOSFETs -- Silicon-on-insulator (SOI) -- Breakdown voltage (BV) -- Specific on-resistance; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2018.09.007
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: The design and optimisation of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 100 V) is carried out with physically based commercial 3-D TCAD device simulations using Silvaco. We calibrate drift-diffusion simulations to experimental characteristics of the SJ multi-gate MOSFET (SJ-MGFET) aiming at improving drive current, breakdown voltage (BV), and specific on-resistance (R on, sp ). We investigate variations in the device architecture and improve device performance by optimizing doping profile under charge imbalance. The SJ-MGFET, using a folded alternating U-shaped n / p – SJ drift region pillar width of 0.3 μm with a trench depth of 2.7 μm achieves specific on-resistance (R on, sp ) of 0.21 mΩ.cm 2 at a BV of 65 V. In comparison with conventional planar gate SJ-LDMOSFETs, the optimised SJ-MGFET gives 68% reduction in R on, sp and 41% increase in a saturation drain current at a drain voltage of 5 V and a gate voltage of 10 V.