A tunnel FET compact model including non-idealities with verilog implementation. (December 2018) - Sajjad, Redwan N.; Radhakrishna, Ujwal; Antoniadis, Dimitri A.
Highlights: A tunnel FET compact model is developed including crucial non-idealities such as the trap assisted tunneling. The compact model is tested against experimental data achieving excellent fit. Compact expressions describing details of TFET device physics are developed. A Verilog-A model is developed on the basis of the compact model and simple TFET circuits are simulated. The compact model can be used to benchmark TFET technology for varying degrees of non-idealities and other device parameters. Abstract: We present a compact model for Tunnel Field Effect Transistors (TFET), that captures several non-idealities such as the Trap Assisted Tunneling (TAT) originating from interface traps ( D it ), along with Verilog-A implementation. We show that the TAT, together with band edge non-abruptness known as the Urbach tail, sets the lower limit of the sub-threshold swing and the leakage current at a given temperature. Presence of charged trap states also contributes to reduced gate efficiency. We show that we can decouple the contribution of each of these processes and extract the intrinsic sub-threshold swing from a given experimental data. We derive closed form expressions of channel potential, electric field and effective tunnel energy window to accurately capture the essential device physics of TFETs. We test the model against recently published experimental data, and simulate simple TFET circuits using the Verilog-A model. The compact model provides a framework for TFET technology projections with improved device metrics such as better electrostatic design, reduced TAT, material with better transport properties etc.