A framework for power estimation and reduction in multi-core architectures using basic block approach. (1st January 2013)

• Record Type: Journal Article
• Authors: Rajasekhara Babu, M.; Venkata Krishna, P.; Khalid, M.
• Is Part Of: International journal of communication networks and distributed systems. Volume 10:Number 1(2013)
• Page Start: 40
• Page End: 51
• Publication Date: 2013-01-01
• Subjects: framework -- parallelisation -- power estimation -- power reduction -- multi-core; Computer networks -- Periodicals; Telecommunication systems -- Periodicals; Electronic data processing -- Distributed processing -- Periodicals; 004.6
• Languages: English
• ISSNs: 1754-3916

Abstract

In recent scenarios, power consumption is critical for battery operated devices. There are wide varieties of implementations of dynamic voltage scaling (DVS) algorithm to reduce energy or power. This paper presents a framework called PERMA, power estimator and reducer for multi-core architectures. The PERMA estimates power consumption and suggests analytical procedure to reduce power consumption at basic block level rather than at region level using clock cycles of instructions for a particular architecture (x86). PERMA estimates execution time for each basic block for various voltage levels and chooses best out of these. Therefore, PERMA evaluates the extent to which the voltage can be varied for various Basic Blocks to reduce power consumption without degrading execution time. Finally, it is tested for matrix multiplication of various sizes. There is an improvement in the execution time up to 33.43% with PERMA and 21.89% without PERMA.