Generalized nonisolated high step‐up DC‐DC converter with reduced voltage stress on devices. (21st June 2018)

• Record Type: Journal Article
• Authors: Jalilzadeh, Tohid; Babaei, Ebrahim; Maalandish, Mohammad
• Is Part Of: International journal of circuit theory and applications. Volume 46:Number 11(2018)
• Page Start: 2053
• Page End: 2078
• Publication Date: 2018-06-21
• Subjects: high step‐up DC‐DC converter -- boost DC‐DC converter -- low voltage stress; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2506
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: In this paper, a nonisolated high step‐up DC‐DC converter with low voltage stress on power devices is proposed. The proposed structure consists of a switch and n stages of inductor‐capacitor‐diode cells. The proposed topology combines the boost converter with the self‐lift circuit. Increasing the number of inductor‐capacitor‐diode cells leads to higher voltage gain with a small value of the switch duty cycle, which increases the controllability of the converter. Moreover, by increasing the number of stages, the normalized voltage stress of the power devices is reduced. As a consequence, the metal‐oxide‐semiconductor field‐effect transistor switch with low R DS‐on and devices with low nominal voltage can be used in the proposed converter. Furthermore, due to the existence of one switch, the proposed converter has a simple control system. The analysis of the voltage and current stresses of the power devices is carried out. The circuit performance is compared with other proposed topologies in the literature in voltage gain and normalized voltage stress. Finally, to evaluate the performance of the proposed converter, the experimental results are provided. Abstract : In this paper, a generalized DC‐DC converter structure with high voltage gain and reduced normalized voltage stress across the power devices is proposed. The suggested converter utilizes n stages of inductor‐capacitor‐diode cells so that by increasing n, the voltage gain with a low duty cycle can be achieved and the normalized voltage stress across the devices is reduced. The circuit performance is compared with other topologies in the literature, and finally, experimental results are provided.