Power gating architecture implementation inside clock period to reduce power. (1st January 2014)

• Record Type: Journal Article
• Authors: Nath, Debanjali; Choudhury, Priyanka; Nag, Abhishek; Pradhan, Sambhu Nath
• Is Part Of: International journal of computer aided engineering and technology. Volume 6:Number 3(2014)
• Page Start: 310
• Page End: 323
• Publication Date: 2014-01-01
• Subjects: within-clock -- architecture -- power gating -- leakage -- isolation; Computer-aided engineering -- Periodicals; 620.00285
• Languages: English
• ISSNs: 1757-2657

Abstract

In today's nanometre regime of device dimension, leakage power has become comparable to dynamic power. Along with the other leakage reduction techniques, power gating is a technique which is used to reduce standby leakage and dynamic power by shutting down the power supply of the inactive block of the circuit but the active blocks continues to dissipate power. It has been observed that there is a scope of using power gating in active block to reduce run time leakage. If the operating frequency is lower than the maximum operating frequency of the circuit, then within clock period there is a certain portion which is idle and in this period power gating may be applied. This paper concerns about the implementation of power gating in this idle time of the clock. Architecture of this power gating technique designed to work within the clock period termed as 'within-clock power gating' (WCPG) for minimising leakage and total power of the sequential circuits during active mode of operation has been proposed in this paper. In this architecture an ISCAS89 benchmark circuit has been implemented. Power results have been reported for different frequencies. Simulation of the implemented architecture in CADENCE VLSI tool at 45 nm technology shows up to 85% saving in leakage and around 10% saving in total power compared to the no power gating at 2.5 MHz frequency.