A comprehensive comparison between LE and LM-based methodologies for optimisation of digital circuits. (1st January 2013)

• Record Type: Journal Article
• Authors: Singh, Kunwar; Tiwari, Satish Chandra; Gupta, Maneesha
• Is Part Of: International journal of circuits and architecture design. Volume 1:Number 1(2013)
• Page Start: 89
• Page End: 113
• Publication Date: 2013-01-01
• Subjects: VLSI -- digital CMOS circuits -- logical effort theory -- Levenberg-Marquardt algorithm -- power-delay product -- power-delay-area product; Electronic circuit design -- Periodicals; Electronic circuit design -- Mathematical models -- Periodicals; Computer-aided design -- Periodicals; Computer engineering -- Periodicals; 621.381505
• Languages: English
• ISSNs: 2051-7025

Abstract

This paper presents a comprehensive comparison between Levenberg-Marquardt (LM) and logical effort (LE) theory-based optimisation techniques. While LM is a classical approach for optimisation and is embedded in SPICE, logical effort-based approach is contemporary, design specific and needs simple back of the envelope calculations for optimisation of digital circuits. Both the approaches have been used by digital circuit designers in the literature for comparing a proposed digital circuit with the existing designs while optimising any given design for timing, power and area parameters. The goal of writing this paper is to make digital system designers gain an insight into the procedures used for optimising digital circuits while at the same time a well-defined approach using LM algorithm is provided that can be easily automated with the current generation CAD tools. For the purpose of comparison some standard circuits were chosen and optimised for minimum PDP and PDAP. SPICE simulations have been extensively used for comparing the two methodologies in a 180 nm\1.8 V CMOS technology.