21%-Efficient n-type Rear-junction PERT Solar Cell with Industrial Thin 156mm Cz Single Crystalline Silicon Wafer. (August 2015)

• Record Type: Journal Article
• Authors: Cho, Jinyoun; Shin, Hae-Na-Ra; Lee, Jieun; Choi, Yoonseok; Lee, Jongchul; Oh, Hoon; Kim, Taejun; Hwang, Myungick; Cho, Eun-Chel
• Is Part Of: Energy procedia. Volume 77(2015)
• Page Start: 279
• Page End: 285
• Publication Date: 2015-08
• Subjects: Solar cell -- PERT -- n-type -- boron -- APCVD -- Rear junction -- Surface concentration; Power resources -- Congresses; Power resources -- Periodicals; Power resources; Conference proceedings; Periodicals; 333.7905
• DOI: 10.1016/j.egypro.2015.07.039
• Languages: English
• ISSNs: 1876-6102

Abstract

Abstract: We have achieved 21.2% efficiency, and 670 mV open-circuit voltage(calibrated in Fraunhofer ISE) of n-type rear junction(RJ) PERT (Passivated Emitter Rear Totally-diffused) solar cell with plated Ni/Ag contacts, Al2 O3 rear passivation, and screen-printed local Al BSF on industrial 180 μm-thickness 6-inch n-type Czochralski (Cz) single crystalline silicon wafer. Also 21.0% efficiency and 669 mV open-circuit voltages was achieved with 125 μm-thickness wafer. Effects of borosilicateglass (BSG) deposited by APCVD in different B2 H6 gas flow rate and the influence of O2 addition during furnace tube anneal were studied in terms of not only boron emitter quality but also impact on the cell Voc and FF. We found that, at fixed diffusion temperature, surface boron concentration could be controlled mainly by changing B2 H6 flow rate during BSG deposition by APCVD and subsidiary by O2 addition in the tube furnace anneal. Additionally, as risks of n-type mass production, the 6" n-type wafer quality deviation issue and thin wafer related process issues were discussed.