DARE: Data-Access Aware Refresh via spatial-temporal application resilience on commodity servers. (January 2018)

• Record Type: Journal Article
• Authors: Chalios, Charalampos; Georgakoudis, Giorgis; Tovletoglou, Konstantinos; Karakonstantis, George; Vandierendonck, Hans; Nikolopoulos, Dimitrios S
• Other Names: Dongarra Jack guest-editor.; Tourancheau Bernard guest-editor.
• Is Part Of: International journal of high performance computing applications. Volume 32:Number 1(2018)
• Page Start: 74
• Page End: 88
• Publication Date: 2018-01
• Subjects: Approximate computing -- DRAM -- operating system -- application resilience -- scheduling; High performance computing -- Periodicals; Supercomputers -- Periodicals; 004.1105
• DOI: 10.1177/1094342017718612
• Languages: English
• ISSNs: 1094-3420

Abstract

Power consumption and reliability of memory components are two of the most important hurdles in realizing exascale systems. Dynamic random access memory (DRAM) scaling projections predict significant performance and power penalty due to the conventional use of pessimistic refresh periods catering for worst-case cell retention times. Recent approaches relax those pessimistic refresh rates only on ``strong'' cells, or build on application-specific error resilience for data placement. However, these approaches cannot reveal the full potential of a relaxed refresh paradigm shift, since they neglect additional application resilience properties related to the inherent functioning of DRAM. In this article, we elevate Refresh-by-Access as a first-class property of application resilience. We develop a complete, non-intrusive system stack, armed with low-cost Data-Access Aware Refresh (DARE) methods, to facilitate aggressive refresh relaxation and ensure non-disruptive operation on commodity servers. Essentially, our proposed access-aware scheduling of application tasks intelligently amplifies the impact of the implicit refresh of memory accesses, extending the period during which hardware refresh remains disabled, while limiting the number of potential errors, hence their impact on an application's output quality. The stack, implemented on an off-the-shelf server and running a full-fledged Linux OS, captures for the first time the intricate time-dependent system and data interactions in the presence of hardware errors, in contrast to previous architectural simulations approaches of limited detail. Results demonstrate that by applying DARE, it is possible to completely disable hardware refresh, with minor quality loss that ranges from 2% to 18%.