A 45‐ to 57‐GHz low‐power amplifier in 90 nm bulk CMOS. Issue 11 (23rd August 2017) - Su, Guodong; Sun, Lingling; Wen, Jincai; Liu, Jun; Gao, Haijun; Zhang, Le
Abstract: In this article, a novel two‐stage 45–57 GHz low‐power amplifier is presented and implemented in a 90‐nm bulk CMOS technology. The crossing‐capacitor neutralization technique is adopted to improve the gain and isolation of the amplifier. Meanwhile, the low‐loss transmission line and on‐chip transformer are designed for the matching networks. The measurement results show that the proposed amplifier achieves 3‐dB gain bandwidth of 12 GHz, from 45 to 57 GHz. The maximum small‐signal gain of this amplifier is 7.2 dB at 48.4 GHz, and the output 1‐dB compression power is −6.8 dBm at 48.4 GHz. This amplifier consumes total power of 5.52 mW under 1.2 V voltage supply.