Subthreshold CMOS transistors are largely immune to magnetic field effects when operated above 11 T. Issue 2 (7th June 2015) - Höfflin, Jens; Sander, Christian; Gieschke, Pascal; Greiner, Andreas; Korvink, Jan G.
ABSTRACT: We report on measurements of n ‐channel field‐effect transistor structures with multiple drain/source contacts, fabricated in a commercial complementary metal‐oxide‐semiconductor (CMOS) technology, at high magnetic field strengths. The focus lies on field dependent effects such as the Hall effect to better understand how these key electronic devices behave when their embedding circuits are immersed in strong magnetic fields. In addition, measurement results of relevant electrical parameters for circuit design, i.e., the saturation current of I DS as well as the slope of I DS and threshold voltage V t will be shown. The results are in agreement with theory and it is possible to predict the Hall voltage as well as the channel resistance. This allows to simulate noise behavior of amplifiers using silicon MOSFETs in high magnetic fields. The measurements show that, electrically, CMOS transistors operated in subthreshold mode are largely immune to magnetic field effects when operated above 11 T. © 2015 Wiley Periodicals, Inc. Concepts Magn Reson Part B (Magn Reson Engineering) 45B: 97–105, 2015