A hierarchically defined fault pattern generator using genetic algorithm. (29th March 2010)

• Record Type: Journal Article
• Authors: Sangwan, Dhiraj; Kumar, Rajesh; Kumar, Mukesh
• Is Part Of: International journal of adaptive and innovative systems. Volume 1:Number 2(2010)
• Page Start: 139
• Page End: 157
• Publication Date: 2010-03-29
• Subjects: hierarchy -- test simulators -- delay faults -- genetic algorithms -- GAs -- reference tables -- award number -- fault pattern generators -- adaptive mutation rate -- simulation; Adaptive computing systems -- Periodicals; Computer systems -- Technological innovations -- Periodicals; Systems software -- Periodicals; 004
• Languages: English
• ISSNs: 1740-2107

Abstract

Test generation using fault algorithms is a complex procedure. This paper presents a hierarchical approach for test vector generation, which searches for a compact set of test patterns, in an otherwise large search space. Genetic algorithms (GAs) have been effective in solving many search and optimisation problems. Since test generation is a search process over a large vector space, it is an ideal candidate for GAs. The GA evolves candidate test vectors and sequences, using a fault simulator to compute the fitness of each candidate test. Various GA parameters are studied, including population size, fitness function and mutation rate, as well as selection and crossover schemes. The search for fitter members is possible by modifying a reference table. The main focus in this paper is on the hierarchical expansion of the module into its constituent modules and the fault analysis would be performed only on those submodules which give faulty responses. The variable crossover and mutation rates help in not being trapped in local minima. The different award numbers allows us in focussing on those test sets which give superior detection possibilities with respect to others.