Analysis and improvement of ramp gain error in single-ramp single-slope ADCs for CMOS image sensors. (December 2016)

• Record Type: Journal Article
• Authors: Cheng, Xu; Zeng, Xiaoyang; Feng, Qi
• Is Part Of: Microelectronics journal. Volume 58(2016)
• Page Start: 23
• Page End: 31
• Publication Date: 2016-12
• Subjects: CMOS image sensor (CIS) -- Analog-to-digital converter (ADC) -- Column-parallel ADC -- Single-slope ADC -- Two-step ADC; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2016.10.006
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: The single-ramp single-slope (SRSS) analog-to-digital converter (ADC) is a promising candidate for column-parallel architectures. This paper, for the first time, quantitatively analyzes the ramp gain error in the ramp-input stage (RIS) that is the crucial component in such ADC, and verifies it using behavior model simulation. Then, a novel active RIS is proposed to alleviate the ramp gain error. With an active feedback loop, the ramp gain becomes a product of two reciprocal ratios of capacitance, whose departure from unity is attributed to the relative deviations rather than the absolute values in the conventional passive RIS. The proposed concept is designed and verified by simulations in a 0.18-μm CMOS process.