A non-blocking wavelength routing ONoC based on two-dimension bus architecture. (August 2016)

• Record Type: Journal Article
• Authors: Zhang, Bowen; Gu, Huaxi; Tan, Wei; Wang, Xiaolu; Song, Liang; Hao, Qinfen
• Is Part Of: Microelectronics journal. Volume 54(2016)
• Page Start: 59
• Page End: 66
• Publication Date: 2016-08
• Subjects: Optical network-on-chip -- Two-dimension bus architecture -- Wavelength routing -- Netrace simulation; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2016.05.010
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: With the improvement of silicon-based optical devices and on-chip optical technologies, optical network-on-chip (ONoC) is becoming a significant interconnection solution for its high bandwidth, low network latency and efficient energy utilization. Some bus-based ONoCs face the problems of high bus congestion, low network utilization, which leads to high network latency and an extra overhead in power dissipation. In this paper, a non-blocking wavelength routing ONoC based on two-dimension bus architecture (2DWR-bus) is proposed to solve the problem face by previous bus-based ONoCs, realize multiple IP cores communicating with the same destination IP core simultaneously. The network simulation is carried out for the 16 cores and 64 cores ONoC under synthetic traffics. The end-to-end (ETE) delay and saturation throughput performance are evaluated and compared between 2DWR-bus and similarly-configured ONoCs. Netrace is used in the simulation to evaluate the network performance under realistic scientific application benchmarks. The insertion loss and required laser power for 2DWR-bus is calculated and made a comparison. The evaluation result shows that 2DWR-bus ONoC has better network performance when compared with other equivalent ONoCs, especially under high network offered load.