Bit-width-aware constant-delay run-time Accuracy Programmable Adder for error-resilient applications. (April 2016)

• Record Type: Journal Article
• Authors: Garg, Bharat; Dutt, Sunil; Sharma, G.K.
• Is Part Of: Microelectronics journal. Volume 50(2016)
• Page Start: 1
• Page End: 7
• Publication Date: 2016-04
• Subjects: Approximate computing -- Error-resilient applications -- Approximate adder -- Speed-Power-Accuracy-Area (SPAA) trade-off; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2016.01.002
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Error-resilient applications such as image, audio and video processing adopt the concept of approximate computing to decorate delay, power and area metrics at the cost of accuracy. Approximate computing relaxes the exact equivalence between the design specifications and the design implementation to achieve Speed-Power-Accuracy-Area (SPAA) trade-off. In this paper, we propose a bit-width-aware constant-delay run-time Accuracy Programmable Adder (APA) in which the probability of input combinations exhibiting accurate results is programmable and adaptively controlled by the Number of Iterations ( NoIs ). Simulation results based on the PTM 32 nm CMOS technology suggest that the proposed approach attains tremendous improvements in delay, power and area metrics with a trivial degradation in the output quality. The proposed APA shows 3.4 × improvement in performance and 41.5% reduction in area over the best known accuracy configurable adder. Even with 100% accuracy, a 32-bit APA improves delay, power and area by 33.92%, 23.04% and 17.44%, respectively, over Ripple Carry Adder (RCA). We also demonstrate an APA embedded error-resilient JPEG encoder architecture in order to inspect the efficacy of the proposed approach in real-time Digital Signal Processing (DSP) applications.