Two-path inverter-based low noise amplifier for 10–12 GHz applications. (April 2016) - Yarahmadi, Ahmad; Jannesari, Abumoslem
Abstract: This paper presents a two-path inverter-based low-noise-amplifier (LNA) in TSMC 0.18 µm CMOS technology for 10–12 GHz frequency band applications. The primary path provides a flat and high enough gain within the interested frequency band. The secondary path ensures the input impedance matching for the proposed LNA. A peaking inductor is applied to the gate of inverters NMOS transistor. With this technique, the parasitic capacitance of MOS transistors will be appropriately compensated at high frequencies. Furthermore, resistive shunt feedback is applied to CMOS inverters in order to extend the amplifier bandwidth. The feedback resistor makes the LNA to be a self-biased structure. The proposed LNA consumes 10.3 mW from a 1.8 V supply. The amplifier gain is high enough and S 21 =12.8 dB while the gain flatness is 0.55 dB in the whole frequency band. The structure is optimized for minimum noise figure (NF) and the NF is 2.1–2.3 dB within the bandwidth. The input impedance is matched and S 11 is less than −10 dB. The linearity of the LNA is sufficient and IIP3 is equal to −11 dB m. Highlights: A CMOS inverter based two-path LNA for 10-12 GHz frequency band is presented. The primary path provides required high frequency flat gain. The secondary path ensures the wideband input impedance matching. The bandwidth extension is achieved with resistive shunt feedback.