A signal pre-processing algorithm designed for the needs of hardware implementation of neural classifiers used in condition monitoring. (September 2015)

• Record Type: Journal Article
• Authors: Dabrowski, Dariusz; Hashemiyan, Zahra; Adamczyk, Jan
• Is Part Of: Measurement. Volume 73(2015:Sep.)
• Page Start: 576
• Page End: 587
• Publication Date: 2015-09
• Subjects: Condition monitoring -- Planetary gears -- Neural networks -- FPGA -- Signal processing; Weights and measures -- Periodicals; Measurement -- Periodicals; Measurement; Weights and measures; Periodicals; 530.8
• DOI: 10.1016/j.measurement.2015.06.004
• Languages: English
• ISSNs: 0263-2241

Abstract

Highlights: Signal pre-processing algorithm designed for condition monitoring. Algorithm can be performed in real-time conditions. Implementation of the algorithm does not require many resources of FPGAs. Algorithm resistant to small speed fluctuations of monitored object. Features estimated by the algorithm can serve as an input to a neural network. Abstract: Gearboxes have a significant influence on the durability and reliability of a power transmission system. Currently, extensive research studies are being carried out to increase the reliability of gearboxes working in the energy industry, especially with a focus on planetary gears in wind turbines and bucket wheel excavators. In this paper, a signal pre-processing algorithm designed for condition monitoring of planetary gears working in non-stationary operation is presented. The algorithm is dedicated for hardware implementation on Field Programmable Gate Arrays (FPGAs). The purpose of the algorithm is to estimate the features of a vibration signal that are related to failures, e.g. misalignment and unbalance. These features can serve as the components of an input vector for a neural classifier. The approach proposed here has several important benefits: it is resistant to small speed fluctuations up to 7%, it can be performed in real-time conditions and its implementation does not require many resources of FPGAs.