Cite
HARVARD Citation
Khurshid, B. et al. (2016). Technology optimised fixed-point bit-parallel multiplier for LUT-based FPGAs. International journal of high performance systems architecture. pp. 28-35. [Online].
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Khurshid, B. et al. (2016). Technology optimised fixed-point bit-parallel multiplier for LUT-based FPGAs. International journal of high performance systems architecture. pp. 28-35. [Online].