Design of quantum cost efficient reversible multiplier using Reed-Muller expressions. (2016)

• Record Type: Journal Article
• Authors: Pankaj, N. Rajeev; Venugopal, P.; Mortha, Prasanthi
• Is Part Of: International journal of computing science and mathematics. Volume 7:Number 3(2016)
• Page Start: 221
• Page End: 228
• Publication Date: 2016
• Subjects: reversible logic gates -- Reed-Muller expressions -- positive Davio -- negative Davio -- reversible multipliers -- quantum cost -- garbage outputs -- constant inputs -- reversible logic design -- simulation; Mathematics -- Periodicals; Computer science -- Periodicals; Mathematics -- Data processing -- Periodicals; 510.285
• Languages: English
• ISSNs: 1752-5055

Abstract

Reversible logic design is one of the emerging trends in recent years as it is good for low power design. A good number of design methods for reversible multipliers were proposed earlier. In this paper, two bit reversible multiplier was designed using Reed-Muller expressions, and this new reversible multiplier was used to design 4-bit reversible multiplier. The results save 16.9% of quantum cost (QC), 38.5% of garbage outputs (GOs) and 10.7% of constant inputs (CIs) compared to earlier designs. The simulations are done on Xilinx 10.1 and are presented. The methodology is extended for the design of 8-bit and 16-bit multipliers and the reversible logic metrics were presented for different bit lengths.