A CMOS symmetric self-biased voltage reference. (October 2018)

• Record Type: Journal Article
• Authors: Park, Minseon; Park, Sung Min
• Is Part Of: Microelectronics journal. Volume 80(2018)
• Page Start: 28
• Page End: 33
• Publication Date: 2018-10
• Subjects: CMOS -- Constant-gm -- Modified cascode -- PVT variation -- Self-biased -- Voltage reference; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2018.08.002
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper presents a novel CMOS voltage reference circuit named symmetric self-biased voltage reference (SSVR), which enables not only to discard the voltage headroom issue of a conventional constant-g m current source and the inevitable need of an extra bias in a modified constant-g m current source, but also to maintain stable bias voltages with strong tolerance against significant variations of power supply and temperature. Test chips of the SSVR were implemented by using a 0.11-μm CMOS process. Measured results demonstrate that the symmetric configuration of the proposed SSVR helps to achieve constant voltage references against the V DD variation from 0.7 to 1.2 V and the temperature variation from −15 °C to 125 °C. The fabricated chip consumes constant 18.5 μA currents for 0.7 ∼ 1.0-V supply voltages and its core occupies the area of 0.04 × 0.047 mm 2 .