Acceleration and energy consumption optimization in cascading classifiers for face detection on low‐cost ARM big. LITTLE asymmetric architectures. (3rd September 2018)

• Record Type: Journal Article
• Authors: Corpas, Alberto; Costero, Luis; Botella, Guillermo; Igual, Francisco D.; García, Carlos; Rodríguez, Manuel
• Other Names: Fernàndez‐Berni Jorge guestEditor.; Carmona‐Galàn Ricardo guestEditor.; Sicard Gilles guestEditor.; Dupret Antoine guestEditor.
• Is Part Of: International journal of circuit theory and applications. Volume 46:Number 9(2018)
• Page Start: 1756
• Page End: 1776
• Publication Date: 2018-09-03
• Subjects: AMP -- big. LITTLE ARM asymmetric architecture -- energy efficiency -- face detection -- Odroid XU4 -- OmpSs -- OpenMP -- Raspberry Pi -- task parallelization -- Viola‐Jones algorithm; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2552
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: This paper proposes a mechanism to accelerate and optimize the energy consumption of a face detection software based on Haar‐like cascading classifiers, taking advantage of the features of low‐cost asymmetric multicore processors (AMPs) with limited power budget. A modelling and task scheduling/allocation is proposed in order to efficiently make use of the existing features on big. LITTLE ARM processors, including (1) source‐code adaptation for parallel computing, which enables code acceleration by applying the OmpSs programming model, a task‐based programming model that handles data‐dependencies between tasks in a transparent fashion; (2) different OmpSs task allocation policies which take into account the processor asymmetry and can dynamically set processing resources in a more efficient way based on their particular features. The proposed mechanism can be efficiently applied to take advantage of the processing elements existing on low‐cost and low‐energy multi‐core embedded devices executing object detection algorithms based on cascading classifiers. Although these classifiers yield the best results for detection algorithms in the field of computer vision, their high computational requirements prevent them from being used on these devices under real‐time requirements. Finally, we compare the energy efficiency of a heterogeneous architecture based on AMPs with a suitable task scheduling with that of a homogeneous symmetric architecture. Abstract : We proposed a mechanism to accelerate and optimize the energy consumption of a face detection based on Haar‐like classifiers, taking advantage of the features of low‐cost asymmetric multicore processors (AMPs) with limited power budget. A modelling and task scheduling/allocation is proposed to efficiently leverage the existing features on big. LITTLE ARM processors, such as source‐code adaptation for parallel computing, and different OmpSs task allocation policies which take into account the processor asymmetry which dynamically set resources in an efficient way.