Tri-gate InGaAs-OI junctionless FETs with PE-ALD Al2O3 gate dielectric and H2/Ar anneal. (January 2016) - Djara, Vladimir; Czornomaz, Lukas; Deshpande, Veeresh; Daix, Nicolas; Uccelli, Emanuele; Caimi, Daniele; Sousa, Marilyne; Fompeyrine, Jean
Abstract: We present a tri-gate In0.53 Ga0.47 As-on-insulator (InGaAs-OI) junctionless field-effect transistor (JLFET) architecture. The fabricated devices feature a 20-nm-thick n -In0.53 Ga0.47 As channel doped to 10 18 /cm 3 obtained by metal organic chemical vapor phase deposition and direct wafer bonding along with a 3.5-nm-thick Al2 O3 gate dielectric deposited by plasma-enhanced atomic layer deposition (PE-ALD). The PE-ALD Al2 O3 presents a bandgap of 7.0 eV, a k -value of 8.1 and a breakdown field of 8–10.5 MV/cm. A post-fabrication H2 /Ar anneal applied to the PE-ALD Al2 O3 /In0.53 Ga0.47 As-OI gate stack yielded a low density of interface traps ( Dit ) of 7 × 10 11 /cm 2 eV at Ec − E = −0.1 eV along with lower border trap density values than recently reported PE-ALD bi-layer Al2 O3 /HfO2 and thermal ALD HfO2 gate stacks deposited on In0.53 Ga0.47 As. The H2 /Ar anneal also improved the subthreshold performance of the tri-gate InGaAs-OI JLFETs. After H2 /Ar anneal, the long-channel (10 μm) device featured a threshold voltage ( VT ) of 0.25 V, a subthreshold swing (SS) of 88 mV/dec and a drain-induced barrier lowering (DIBL) of 65 mV/V, while the short-channel (160 nm) device exhibited a VT of 0.1 V, a SS of 127 mV/dec and a DIBL of 218 mV/V. Overall, the tri-gate InGaAs-OI JLFETs showed the best compromise in terms of VT, SS and DIBL compared to the other III–V JLFET architectures reported to date. However, a 15× increase in access resistance was observed after H2 /Ar anneal, significantly degrading the maximum drain current of the tri-gate InGaAs-OI JLFETs.