Design of Testable Adder in Quantum‐dot Cellular Automata with Fault Secure Logic. (February 2017)

• Record Type: Journal Article
• Authors: Goswami, Mrinal; Sen, Bibhash; Mukherjee, Rijoy; Sikdar, Biplab K
• Is Part Of: Microelectronics journal. Volume 60(2017)
• Page Start: 1
• Page End: 12
• Publication Date: 2017-02
• Subjects: Quantum-dot cellular automata (QCA) -- QCA defects -- Parity preserving logic -- Testability -- Nano-electronics; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2016.11.008
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: The rapid advancement of Quantum-dot cellular automata (QCA) technology has moved on to the effective methods for testing these circuits due to its insufficient reliability. The growing demand for fault tolerance and testability attracts more research on it. This paper targets, a novel parity preserving testable adder (t-Adder) in QCA which tackles the internal fault within the gate efficiently resulting a testable circuit. The fault patterns of t-Adder gate under cell deposition defects are investigated. The most striking characteristic of this logic is that it is completely testable for single as well as multiple stuck-at faults using only three test vectors. Also, the functionality and the defect tolerance of the proposed t-Adder under the Path Fault Secure (PFS) scheme are studied which ensures more reliability. A comprehensive power dissipation analysis, as well as structural analysis of the testable logic gates, is performed which signifies the dominance of t-Adder in low power consumption. Further, the programmable feature of t-Adder is utilized to implement an efficient ALU, realizing 10 important functions along with addition operation. The design of QCA layout, as well as functional verification of the proposed design, is performed using the QCADesigner and HDLQ tool respectively whereas the power dissipation is evaluated using QCAPro simulator. Abstract : Highlights: A testable parity preserving full adder (t-Adder) is designed considering its primary outputs. Reliability issue is addressed with the success of 100% fault coverage with only 3 (three) test vectors. The power dissipation of the t-Adder is analysed which ensures low power consumption. To make robust fault secure t-Adder, path fault secure (PFS) scheme (first time in QCA circuit) is riveted to it. Further, t-Adder is used to design a simple testable ALU with high logical depth.