Two-step pulse-shrinking time-to-digital converter. (February 2017)

• Record Type: Journal Article
• Authors: Park, Young Jun; Yuan, Fei
• Is Part Of: Microelectronics journal. Volume 60(2017)
• Page Start: 45
• Page End: 54
• Publication Date: 2017-02
• Subjects: Time-to-digital converters (TDCs) -- Pulse-shrinking TDCs; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2016.11.015
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper presents a two-step pulse-shrinking time-to-digital converter (TDC) consisting of a 4-stage coarse pulse-shrinking TDC with per-stage shrinkage 1 ns and a 4-stage fine pulse-shrinking TDC with per-stage shrinkage 250 ps. A simple residual time extraction scheme is proposed to extract the residual pulse of the coarse TDC. The characteristics of the TDC including mismatch and noise-induced timing errors, timing errors of delay blocks, conversion time, power consumption, and silicon consumption are analyzed in detail. The proposed TDC was implemented in an IBM 130 nm 1.2 V CMOS technology. Simulation results show that the proposed TDC offers 1.4 ns conversion time, 1 LSB DNL and INL, and figure-of-merit (FoM) of 0.163 pJ/step. Some measurement results of the proposed TDC are also presented.