A comparative study of steganography designs based on multiple FPGA platforms. (2016)

• Record Type: Journal Article
• Authors: Mohd, Bassam J.; Hayajneh, Thaier; Khalaf, Zaid Abu; Vasilakos, Athanasios V.
• Is Part Of: International journal of electronic security and digital forensics. Volume 8:Number 2(2016)
• Page Start: 164
• Page End: 190
• Publication Date: 2016
• Subjects: information security -- field-programmable gate arrays -- steganography design -- multiple FPGA -- data hiding -- spatial steganography -- modelling -- least significant bit -- LSB -- performance measures; Computer crimes -- Periodicals; Computer crimes -- Investigation -- Periodicals; Computer security -- Periodicals; Electronic commerce -- Law and legislation -- Periodicals; Information warfare -- Periodicals; 005.805
• Languages: English
• ISSNs: 1751-911X

Abstract

Steganography methods conceal covert messages inside communicated data. Field-programmable gate array (FPGA) hardware implementation provides speed, flexibility and configurability. It is extremely difficult to compare published results from different platforms and technologies. The goal of our research work is to mitigate the dependency by examining implementations from multiple FPGA platforms. The research studies the implementations of 12 spatial steganography methods using Altera and Xilinx FPGAs. The methods include mix-bit LSB, least significant bit (LSB), random LSB and texture-based algorithms. The objective of the research is to develop platform-independent resources, timing, power and energy models; to empower future steganography research. Further, the article evaluates steganography methods using typical performance metrics as well as a novel performance metric. The results suggest that the mix-bit methods exhibit good performance across most of the metrics. However, when image quality is a concern, the two-bit LSB is the front runner.