Cite
HARVARD Citation
Taco, R. et al. (2016). Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI. Solid-state electronics. pp. 185-192. [Online].
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Taco, R. et al. (2016). Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI. Solid-state electronics. pp. 185-192. [Online].