Cross-sectional nanoprobing fault isolation technique on submicron devices. (September 2016) - Tan, P.K.; Yap, H.H.; Chen, C.Q.; Rivai, F.; Zhao, Y.Z.; Zhu, L.; Feng, H.; Tan, H.; He, R.; Wang, D.D.; Huang, Y.M.; Ma, Y.Z.; et al.
Abstract: With continuous scaling on CMOS device dimensions, it is becoming increasingly challenging for conventional failure analysis (FA) methods to identify the failure mechanism at the circuit level in an integrated chip. Scanning Electron Microscopy (SEM) based nanoprobing is becoming an increasingly critical tool for identifying non-visual failures via electrical characterization in current electrical FA metrology for fault isolation since 2006 Toh et al. (2007), Shen et al. (2007), Ng et al. (2012) . Currently, most of the nanoprobing fault isolation is nanoprobe in top-down planar direction, such as nanoprobe on via, contact and metal line. This paper focused on fault isolation of sub-micron devices by nanoprobing on a cross-sectional plane. This is a new application area; it is very useful for sample that cannot perform fault isolation with conventional top-down planar nanoprobing, especially on non-volatile memory that with single transistor memory array that arrange in a vertical direction, such as Magnetic Random Access Memory (MRAM), Phase-Change Random Access Memory (PC-RAM), flash memory and etc. Highlights: A cross-sectional nanoprobing technique is proposed and demonstrated. The technique is especially useful to perform fault isolation on non volatile memory. Fault isolation on Front End and Back End Of Line related issue with this technique was demonstrated. Sample preparation of cross-sectional nanoprobing technique was discussed and explained. The technique also suitable for fault isolation on sample that cannot perform in top-down planar nanoprobing technique.