Potentiality of healing techniques in hot-carrier damaged 28 nm FDSOI CMOS nodes. (September 2016) - Bravaix, A.; Cacho, F.; Federspiel, X.; Ndiaye, C.; Mhira, S.; Huard, V.
Abstract: We have developed the possibility of using healing phases on hot-carrier (HC) degraded transistors from devices to logic cells (1) by the combined effects of oxide charge neutralization and channel shortening (2) using back bias VB sensing effects in forward (FBB) mode in 28 nm FDSOI CMOS node. This is done for DC to AC operations from Input-Output device (EOT = 3.6 nm) to core blocks (EOT = 1.35 nm) leading to an almost complete cure of HC damaged devices for digital application. Continuous or short sequences of healing phases help to regenerate HC degraded parameters (IOn, VT ) offering new perspectives for on time repeatedly cure digital operation as well as under some analog case. Graphical abstract: Fig. 3 (a) Linear IDS curves below/above Vth showing partial healing under HH injection VDS /VGS = 1.8/0.5 V after HE degradation (1.4/1.4 V) in 28FD NMOSFET using 5 alternating DC stress. (b) Time dependence for IDlin, IDSat (VDD, VDD ). Fig. 5: Schematics of healing procedure during AC operation here in N–MOSFETs. A waiting time is enchained to help the healing phase by the amount of relaxation after full overlap AC healing triggered at tswitch (duty = 50%, fAC = f healing). Fig. 6: Inverter stress in IO NMOS showing the accelerated factor AFN for fixed pulse shape tr, f /TAC = 4%. Healing steps increase (1, 10, 1000s) are applied at ts > tswitch using HH injections after each stage leading to a net effect on IDlin and IDSat enlarged with twait . Fig. 12: Degradation of (LVT) RO frequency drift Fosc /Fosc, 0 as a function of ts for 4 ROs (28FD) measured at stress using On the Fly technique at 125 °C. FBB sense application with VB = ± 0.3 V in NMOS and PMOS after 6.10 4 s, cures almost totally the long term AC stressing. Highlights: New healing techniques are used to neutralized hot-carriers damage. Charge neutralization allows to reduce damage under DC and AC operations. Compensating technique is developed by using forward bulk bias in FDSOI. Compensation is demonstrated in transistors and 28 nm CMOS ring-oscillators. These techniques enable to extend lifetime of digital applications.