Impact of resistive paths on NVM array reliability: Application to Flash & ReRAM memories. (September 2016) - Canet, P.; Postel-Pellerin, J.; Aziza, H.
Abstract: In memory technology, size reduction induces consequences in terms of reliability, including an increase in the line resistances and a voltage drop along the line during memory operation. This problem can occur in Flash products during sector erase mode, and in resistive RAM (ReRAM) during forming, reset or word-reading modes. In this paper we apply a simple resistive model to determine the wordline (or bitline) length of a Flash memory (and thus to optimize the Flash memory array's size) or the word length of a ReRAM, according to specific reliability criteria: the threshold voltage drop of cells along a line in a Flash memory sector, or the resistance variation of the cells in a ReRAM word. For the technologies considered in this paper, on the one hand we demonstrate a maximal threshold voltage drop of 2 V for a 4 Gbit Flash array and we provide design recommendations, and on the other hand we demonstrate that a maximal word length of 32 bits for ReRAM can be achievable in a ReRAM matrix. The presented methodology can easily be extended to any memory technology. Highlights: Line resistance induces a voltage drop along a memory line when all the cells are addressed. Iterative model gives the exact voltage distribution along the memory line. Explicit model is fast and accurate with low voltage drop. Both models are helpful to design Flash memory array or ReRAM length.