Performance analysis of Cellular Automata HPC implementations. (November 2015)

• Record Type: Journal Article
• Authors: Millán, Emmanuel N.; Bederian, Carlos S.; Piccoli, María Fabiana; Garino, Carlos García; Bringa, Eduardo M.
• Is Part Of: Computers & electrical engineering. Volume 48(2015)
• Page Start: 12
• Page End: 24
• Publication Date: 2015-11
• Subjects: Hardware counters -- Cellular Automata -- High Performance Computing -- Weak and strong scaling; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2015.09.015
• Languages: English
• ISSNs: 0045-7906

Abstract

Highlights: We present a free open source code for Cellular Automata (CA) using MPI. Weak and strong scaling tests are carried out in 3 different architectures. Performance of our code compares well with performance of other mature HPC codes. Hardware counters are used to help identifying performance issues. Graphical abstract: Abstract: Cellular Automata (CA) are of interest in several research areas and there are many available serial implementations of CA. However, there are relatively few studies analyzing in detail High Performance Computing (HPC) implementations of CA which allow research on large systems. Here, we present a parallel implementation of a CA with distributed memory based on MPI. As a first step to insure fast performance, we study several possible serial implementations of the CA. The simulations are performed in three infrastructures, comparing two different microarchitectures. The parallel code is tested with both Strong and Weak scaling, and we obtain parallel efficiencies of ∼ 75%–85%, for 64 cores, comparable to efficiencies for other mature parallel codes in similar architectures. We report communication time and multiple hardware counters, which reveal that performance losses are related to cache references with misses, branches and memory access.