Design and analysis of RF-low power and low-phase noise CMOS ring oscillator for fully integrated RF communication systems technologies. (2016)

• Record Type: Journal Article
• Authors: Raman, Ashish; Sarin, Rakesh Kumar
• Is Part Of: International journal of information and communication technology. Volume 8:Number 1(2016)
• Page Start: 79
• Page End: 94
• Publication Date: 2016
• Subjects: oscillator stability -- CMOS -- low power -- phase noise -- voltage controlled oscillator -- VCO -- ring oscillator design -- VLSI -- fine tuning -- wireless communications -- oscillator noise -- PLL -- RF communications -- transistor size -- frequency range -- power dissipation -- oscillating frequency -- energy consumption; Information technology -- Periodicals; Computer science -- Periodicals; Telecommunication -- Periodicals; 004.05
• Languages: English
• ISSNs: 1466-6642

Abstract

This manuscript presents the design and analysis of five-stage, low power ring oscillator. The ring oscillator has implemented in 0.18 µm CMOS one-poly six-metal-layer process technology and designed for frequency synthesiser module used in RF communication applications. This work uses a single ended topology and the delay cell is designed with both tail-ahead and tail-current concept for frequency improvement. This work projects the effect of transistor size (w/l) on the important parameters of oscillator viz. frequency and power dissipation. Measurements show that the oscillator covers a frequency range of 0.9-2 GHz. Their analyses demonstrate that the circuit consumes minimum power of 305 µW at 0.9 GHz and maximum 575 µW at 2 GHz oscillating frequency. The designed oscillator occupies an area of 296 * 130 µm² and manifest an improved phase noise level of −111.9 dBc/Hz.