A novel low-energy CNFET-based full adder cell using pass-transistor logic. (2015)

• Record Type: Journal Article
• Authors: Mehrabani, Yavar Safaei; Mirzaee, Reza Faghih; Eshghi, Mohammad
• Is Part Of: International journal of high performance systems architecture. Volume 5:Number 4(2015)
• Page Start: 193
• Page End: 201
• Publication Date: 2015
• Subjects: full adder cells -- pass transistor logic -- PTL -- carbon nanotubes -- CNTs -- CNT field effect transistors -- CNFET -- low energy consumption -- nanoelectronics -- nanotechnology -- voltage drop -- simulation; Computer architecture -- Periodicals; Computer systems -- Periodicals; High performance computing -- Periodicals; 004.205
• Languages: English
• ISSNs: 1751-6528

Abstract

Full adder is the most critical and fundamental computational unit within processors. A new single-bit full adder cell is presented in this paper in order to cell efficiency. The new design is based on pass-transistor logic (PTL) and carbon nanotube field effect transistor (CNFET) technology. This combination resolves the problem of voltage drop in PTL. The proposed structure is an excellent trade-off between speed and power efficiency factors. Simulations are made by Synopsys HSPICE with 32 nm CNFET in various realistic conditions. The results demonstrate that the proposed adder cell outperforms other state-of-the-art designs in terms of energy consumption, and it is an appropriate candidate to be used in large circuits.