FPGA design of EKF block accelerator for 3D visual SLAM. (October 2016)

• Record Type: Journal Article
• Authors: Törtei Tertei, Daniel; Piat, Jonathan; Devy, Michel
• Is Part Of: Computers & electrical engineering. Volume 55(2016)
• Page Start: 123
• Page End: 137
• Publication Date: 2016-10
• Subjects: Visual EKF-SLAM -- SoC -- FPGA -- Co-processor -- AHP; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2016.05.003
• Languages: English
• ISSNs: 0045-7906

Abstract

Highlights: FPGA implementation of computing EKF gain and cross-covariance matrices is proposed. Exploiting cross-covariance matrix symmetry reduces computational and resource costs. EKF innovation matrix dimension allows for simple SA computational designs. Our innovation supports observations of 60 AHP landmarks in real time on Zynq-7020. Proposed hardware accelerator for EKF VO functionality is platform independent. Graphical abstract: Abstract: This paper deals with the evaluation of a dedicated architecture to be integrated into an embedded system typically mounted on a micro-aerial vehicle or on smart devices held by an operator. This system performs an Extended Kalman Filter (EKF) based visual odometry (VO) algorithm. An efficient hardware architecture conceived as a systolic array co-processor for EKF loop acceleration is presented. Due to severe limitations in terms of power consumption, real-time performance and physical characteristics of the system (i.e. compactness and weight), this algorithm is implemented entirely as a System On a programmable Chip (SoC) on the Zynq-7020 device. This heterogeneous (processor with reconfigurable hardware) platform consumes less power than a standard microprocessor and provides powerful parallel data processing capabilities: applying hardware/software (hw/sw) co-design allows real-time throughput with a very low power-per-feature rate.