Programming the Adapteva Epiphany 64-core network-on-chip coprocessor. (July 2017)

• Record Type: Journal Article
• Authors: Varghese, Anish; Edwards, Bob; Mitra, Gaurav; Rendell, Alistair P
• Is Part Of: International journal of high performance computing applications. Volume 31:Number 4(2017)
• Page Start: 285
• Page End: 302
• Publication Date: 2017-07
• Subjects: Network-on-chip -- Epiphany -- stencil -- parallella -- matrix-matrix multiplication; High performance computing -- Periodicals; Supercomputers -- Periodicals; 004.1105
• DOI: 10.1177/1094342015599238
• Languages: English
• ISSNs: 1094-3420

Abstract

Energy efficiency is the primary impediment in the path to exascale computing. Consequently, the high-performance computing community is increasingly interested in low-power high-performance embedded systems as building blocks for large-scale high-performance systems. The Adapteva Epiphany architecture integrates low-power RISC cores on a 2D mesh network and promises up to 70 GFLOPS/Watt of theoretical performance. However, with just 32 KB of memory per eCore for storing both data and code, programming the Epiphany system presents significant challenges. In this paper we evaluate the performance of a 64-core Epiphany system with a variety of basic compute and communication micro-benchmarks. Further, we implemented two well known application kernels, 5-point star-shaped heat stencil with a peak performance of 65.2 GFLOPS and matrix multiplication with 65.3 GFLOPS in single precision across 64 Epiphany cores. We discuss strategies for implementing high-performance computing application kernels on such memory constrained low-power devices and compare the Epiphany with competing low-power systems. With future Epiphany revisions expected to house thousands of cores on a single chip, understanding the merits of such an architecture is of prime importance to the exascale initiative.