A novel memory management method for multi-core processors. (April 2016)

• Record Type: Journal Article
• Authors: Tu, Jih-Fu
• Is Part Of: Computers & electrical engineering. Volume 51(2016)
• Page Start: 184
• Page End: 194
• Publication Date: 2016-04
• Subjects: Multicore -- system-on-chip -- hardwired; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2015.10.009
• Languages: English
• ISSNs: 0045-7906

Abstract

Highlights: Multicore processor based on SoC, configured by Tensilica Xtensa ® LX2, was examined. One core used as the host to control the processor chip. Other used as slave that is an extension of digital signal processing applications. Lowest latency-to-cost ratios by a 32-bit bus interface and 4-entry data queue. Abstract: This study examines a multicore processor based on a system-on-chip (SoC) and configured by a Tensilica Xtensa ® LX2. The multicore processor is a heterogeneous, configurable dual-core processor. In this study, one core was used as the host to control the processor chip, and the other was used as a slave to extend digital signal processing applications. Each core not only owned its local memory, but also shared common data memory. In addition, the proposed multicore processors had a virtual memory. This additional memory supported the processor by enabling it to easily manage complex programs; it also allowed the two cores to access data from the unified data memory of different tasks. For bus management, a bus arbitration mechanism was added to handle the cores and to distribute the priority of asynchronous access requests. The benefits of the proposed structure include avoiding hardwired memory and reducing interface handshaking. To verify the proposed processor, it was simulated on the model level using a Petri net graph, and on the system level using ARM SoC designer tools. In the performance simulation, we found that the lowest latency-to-cost ratios were achieved using a 32-bit bus interface and a 4-entry data queue.