Adaptive instruction codec architecture design for network-on-chip. (April 2016)

• Record Type: Journal Article
• Authors: Lee, Trong-Yen; Huang, Chi-Han; Liu, Min-Jea; Chen, Jhen-Syuan
• Is Part Of: Computers & electrical engineering. Volume 51(2016)
• Page Start: 207
• Page End: 224
• Publication Date: 2016-04
• Subjects: Adaptive instruction codec architecture (AICA) -- Network on chip (NoC) -- FPGA -- Power consumption, and throughput; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2016.02.021
• Languages: English
• ISSNs: 0045-7906

Abstract

Abstract: This work proposes a novel Adaptive Instruction Codec Architecture (AICA) for network-on-chip (NoC) that improves channel utilization to transfer packets and flits, in order to solve issues of power consumption and throughput. The proposed architecture allows multiple packets to be stuffed into a single packet, and thus can transfer more packets than other network interface (NI) in one time unit. Reducing the number of packets for transmission allows the channel to be reused to transfer additional messages, thus improving channel throughput. This architecture reduces the number of packets transmitted, thus indirectly alleviating the deadlock problem. Many repeating and similar instructions are frequently transferred in NoC. The proposed AICA reduces transmission redundancy, and supports process elements (PE) with 16-bit or 64-bit core CPU. Experimental results show that the proposed architecture and algorithms delivers improvement of up to 48.1% on power consumption, and 46.3% on throughput.