Low power CMOS power amplifier design for RFID and the Internet of Things. (May 2016)

• Record Type: Journal Article
• Authors: Zhao, Chenyuan; Liu, Jian; Shen, Fangyang; Yi, Yang
• Is Part Of: Computers & electrical engineering. Volume 52(2016)
• Page Start: 157
• Page End: 170
• Publication Date: 2016-05
• Subjects: CMOS -- Power amplifier -- Transceiver -- Wireless communication; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2015.06.006
• Languages: English
• ISSNs: 0045-7906

Abstract

Abstract: Designing power amplifiers with low power consumption, high efficiency and integration is an important topic with significant impact on communication and circuit research areas. In order to make transceivers more powerful with lower cost and higher integration, a CMOS power amplifier working from 3.5 GHz to 4.5 GHz is proposed. Cascode driver stage is adopted to give the power amplifier high output gain ability. The output stage is designed as Class A, which makes the proposed power amplifier in a significantly high linearity level. Furthermore, this paper gives a comparative study of the performance of different power amplifier classes. Simulation results show that the proposed power amplifier has 31.2% more power added efficiency (PAE) and 12.6 dB output power gain, respectively. The proposed power amplifier has high linearity and efficiency, which are suitable for Radio Frequency Identification (RFID) and Internet of Things (IoT) applications.