Hardware implementation based on FPGA of semaphore management in μC/OS-II real-time operating system. (2015)

• Record Type: Journal Article
• Authors: Zhu, Shi-hai
• Is Part Of: International journal of grid and utility computing. Volume 6:Number 3/4(2015)
• Page Start: 192
• Page End: 199
• Publication Date: 2015
• Subjects: semaphore management -- event control block -- system calls -- field programmable gate arrays -- software hardening -- hardware design -- FPGAs -- real-time operating systems -- simulation; Electronic data processing -- Distributed processing -- Periodicals; Electronic commerce -- Management -- Computer programs -- Periodicals; 004.605
• Languages: English
• ISSNs: 1741-847X

Abstract

Semaphore is a kind of mechanism used in a multithreaded environment to ensure that two or more key code segments are not concurrently invoked. In order to enhance the response capability of real-time operating systems, a hardware design scheme to implement semaphore management based on field programmable gate array is put forward in this paper. We take the μC/OS-II real-time operating system as an example to design hardware logical circuits of semaphore management function module according to its parallel characteristics, and simulation tests under Xilinx ISE software environment are performed. The simulation results show that implementing semaphore management by hardware can obviously improve the execution time of creating/deleting a semaphore, applying for/releasing a semaphore and P/V operations; therefore, the whole reliability of the real-time operating system is greatly improved.