A 1‐Gbps reference‐less burst‐mode CDR with embedded TDC in a 65‐nm CMOS process. (21st May 2018)

• Record Type: Journal Article
• Authors: Wang, Yuan; Jiang, Mengying; Liu, Baoguang; Jia, Song; Zhang, Xing
• Is Part Of: International journal of circuit theory and applications. Volume 46:Number 8(2018)
• Page Start: 1565
• Page End: 1576
• Publication Date: 2018-05-21
• Subjects: burst‐mode -- clock and data recovery (CDR) -- quantization error -- time‐to‐digital converter (TDC); Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2490
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: A reference‐less all‐digital burst‐mode clock and data recovery circuit (CDR) is proposed in the paper. The burst‐mode CDR includes a coarse and a fine time‐to‐digital converter (TDC) with embedded phase generator. A low‐power current‐starved inverter is employed as the delay unit of the fine TDC to acquire the high measurement resolution. A calibration method to diminish the inherent delay is used to reduce the quantization error of the recovery clock. The proposed CDR is fabricated in a 65‐nm CMOS process. Experiment results show that the CDR operates from 0.9 to 1.1 Gbps and have a 13‐bit consecutive identical digits (CIDs) tolerance. Abstract : A reference‐less burst‐mode CDR is proposed in the paper, which includes a coarse and fine TDC with embedded phase generator. An improved current‐starved inverter is employed as the delay unit of the fine TDC to acquire high resolution. A calibration method to diminish the inherent delay is used to reduce the quantization error. The proposed CDR is fabricated in a 65‐nm CMOS process. Experiment results show that the CDR operates from 0.9 to 1.1 Gbps and have a 13‐bit CID tolerance.