CMOS Buffer Design Approach for Low Power and Lower Delay SRAM Design. (2016)

• Record Type: Journal Article
• Authors: Mariyamol, p.p.; Aswathy, N.
• Is Part Of: Procedia technology. Volume 25(2016)
• Page Start: 481
• Page End: 488
• Publication Date: 2016
• Subjects: SRAM peripheral ;CMOS tapper buffer ;CMOS inverter ;Tapering factor ;Leakage power; Technology -- Congresses; Technology -- Periodicals; Engineering -- Congresses; Engineering -- Periodicals; Engineering; Technology; Conference proceedings; Periodicals; 605
• DOI: 10.1016/j.protcy.2016.08.135
• Languages: English
• ISSNs: 2212-0173

Abstract

Abstract: Leakage power dissipation of on-chip SRAM constitutes a significant amount of the total chip power consumption in microprocessors and System on chips. With technology scaling, it is becoming increasingly challenging to maintain the yield while attempting to reduce the leakage power of SRAMs. The sources of SRAM power are the sum of the power consumed by decoders, memory array, write drivers, Sense amplifiers, and I/O line drivers. This paper is mainly focuses on the development of power and delay efficient SRAM structure. The paper describes the comparison of different CMOS tapper buffer topology's as word line drivers while driving large capacitive loads for minimizing power dissipation and propagation delay. The comparison has been designed and simulated using Cadence Virtuoso Spectre in 180 nm technology.