A Low Power Reconfigurable Encoder for Flash ADCs. (2016)

• Record Type: Journal Article
• Authors: Varghese, George Tom; Mahapatra, Kamalakanta
• Is Part Of: Procedia technology. Volume 25(2016)
• Page Start: 574
• Page End: 581
• Publication Date: 2016
• Subjects: Analog to digital Converter -- Flash ADC -- Dynamivc Logic; Technology -- Congresses; Technology -- Periodicals; Engineering -- Congresses; Engineering -- Periodicals; Engineering; Technology; Conference proceedings; Periodicals; 605
• DOI: 10.1016/j.protcy.2016.08.147
• Languages: English
• ISSNs: 2212-0173

Abstract

Abstract: The present analysis suggests a competent low power thermometer code to binary code converter anticipated for a 3 GS/s five bit flash analog to digital converter. The speed and power are the bottle neck parameters in the design of thermometer to binary code converter. With the aim of medium speed and low power dissipation, the first stage of encoder is designed using dynamic logic. To make the code more resilient to bubble errors, the last stage is designed in wallace tree fashion with the help of four full adders. With the use of CADENCE tool, the proposed encoder is designed using 90 nm technology with a power supply of 1.2 V. The simulation results shows that maximum operating frequency of 3 GHz can be accomplished with a power dissipation of 2.424 mW which is a less value in comparison with other methods of implementation. The reconfigurable property of the proposed encoder makes it useful in reconfigurable flash ADCs.