Implementation of Digital Modulator Using Digital Multiplier for Wireless Applications in Verilog and Cadence. (2016)

• Record Type: Journal Article
• Authors: Usha, S.M.; Nataraj, K.R.
• Is Part Of: Procedia technology. Volume 25(2016)
• Page Start: 435
• Page End: 442
• Publication Date: 2016
• Subjects: QPSK -- FPGA -- Cadence -- Verilog -- Booth Multiplier ;WIMAX -- FDMA -- TDMA -- CDMA ;; Technology -- Congresses; Technology -- Periodicals; Engineering -- Congresses; Engineering -- Periodicals; Engineering; Technology; Conference proceedings; Periodicals; 605
• DOI: 10.1016/j.protcy.2016.08.129
• Languages: English
• ISSNs: 2212-0173

Abstract

Abstract: The digital communication is more advantageous than analog communication. Digital components and subsystems are easy to build than analog components. As the implementation in VLSI technology progressed, the cost of the integrated circuits is gradually reduced. The components used in digital communication systems are robust and insensitive to atmospheric conditions and ensures good protection against noise and interference. The digital design offers more flexibility than analog design. The proposed digital Quadrature Phase Shift Keying(QPSK)modulator is based on digital multiplier called booth multiplier. This work is simulatedin Integrated Simulated Environment (ISE), Incisive simulators of Xilinx9.1i and Cadence tool respectively. The code is synthesized using Cadence RTL compiler and implemented on Field Programmable Gate Array (FPGA) spatan3 kit. The performance parameters such as power, area, and timing are analyzed and compared. This proposal gives better results than the conventional method of using analog multiplier for QPSK system.