Performance optimization of real-time video decoding. (August 2018)

• Record Type: Journal Article
• Authors: Sankaraiah, S.; Eswaran, C.
• Is Part Of: Computers & electrical engineering. Volume 70(2018)
• Page Start: 366
• Page End: 379
• Publication Date: 2018-08
• Subjects: Dynamic scheduling -- Speed up -- Cache misses -- Barrier -- Scalability -- Load balancing; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2016.08.022
• Languages: English
• ISSNs: 0045-7906

Abstract

Highlights: The H.264 Video decoder is implemented using Group of Pictures (GOP) level parallelism. With new dynamic scheduling algorithm, no additional thread is required for scheduling. Our new algorithm provides better scalability and dynamic load balance. We have implemented with advanced data structures to reduce the cache misses and latency. High decoder speedup values without degrading the video quality. Abstract: One of the most challenging tasks in the multimedia domain is the full high definition (FHD) video decoding. A high level data parallelization technique using group of pictures (GOP) concept is proposed in this paper for the implementation of the FHD video decoder. Though GOP level parallelism has advantages such as higher scalability and independent frame decoding possibility, its requirement of higher memory resources remains its main drawback. In order to solve the short comings related to the problem of memory issues, a new dynamic memory scheduling algorithm for GOP level parallelism is proposed. This paper focuses on techniques for optimizing the memory requirements and speedup of FHD video decoding with GOP level parallelism. Experimental results show that the proposed dynamic memory scheduling technique reduces elapsed time significantly making real time FHD video decoding possible. Further, the results show that the proposed technique does not result in frame skipping and degradation in video quality. With the proposed technique, speedup values of 1.96, 3.96 and 7.95 are obtained for 2, 4 and 8 core processors respectively which are almost equal to the theoretical values.