Design of low power comparator-reduced hybrid ADC. (September 2018) - Molaei, Hasan; Hajsadeghi, Khosrow; Khorami, Ata
Abstract: This paper presents a new low-power comparator-reduced hybrid ADC. The proposed ADC uses dynamic comparators to perform a high-speed low-power conversion. In order to reduce the offset and kickback noise effect of conventional dynamic comparators, a new low-kickback noise comparator with a high pre-amplifier gain is presented. Two 4bit and 8bit ADCs are designed and simulated in 0.18 μm CMOS technology with 1.8 v supply voltage. INL and DNL of 4bit ADC are less than 0.4 LSB and 0.5 LSB, respectively, while 8bit ADC obtains DNL and INL of 0.83 LSB and 1.3 LSB, respectively. With ENOB of 3.6 bit and 7.2 bit for 4bit and 8bit ADCs, the 4bit ADC consumes only 1.7 mW at the sampling rate of 400 Ms/s and the 8bit ADC consumes 4.6 mW at the 80 MS∕s.