An FPGA-friendly CABAC-encoding architecture with dataflow modelling programming. (18th August 2018)

• Record Type: Journal Article
• Authors: Ding, Dandan; Liu, Fuchang; Qi, Honggang; Yao, Zhengwei
• Is Part Of: Imaging science journal. Volume 66:Number 6(2018)
• Page Start: 346
• Page End: 354
• Publication Date: 2018-08-18
• Subjects: Video -- reconfigurable -- CABAC -- FPGA -- dataflow -- H.265/HEVC; Imaging systems -- Periodicals; 621.36705
• DOI: 10.1080/13682199.2018.1477486
• Languages: English
• ISSNs: 1368-2199

Abstract

ABSTRACT: Video compression standards play an important role in video encoding, transmitting and decoding. To exploit the similarities or commonality among standards, a Reconfigurable Video Coding framework is developed in MPEG by employing a dataflow modelling method to modulate the basic configuration components of encoders or decoders. However, the entropy coding for bitstream generating and parsing during the configuration process is very complex, especially when employing the Context Adaptive Based Arithmetic Coding (CABAC). This paper proposes an optimized 'Producer–Consumer' architecture for CABAC by dataflow modelling. To achieve high-throughput and low-resource consumption, the buffer accessing speed and buffer size in the architecture is analysed and refined. The proposed CABAC is implemented by dataflow language Cal and is synthesized to FPGA. Results show that it can process 3.5 bins/cycle with a 10-byte buffer consumption at a 120 MHz working frequency. It is sufficient for real-time encoding of H.265/HEVC at level 6.2 main tier.