Cite
HARVARD Citation
Yuejun, Z. et al. (2018). An ultra-low power multiplier using multi-valued adiabatic logic in 65 nm CMOS process. Microelectronics journal. pp. 26-34. [Online].
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Yuejun, Z. et al. (2018). An ultra-low power multiplier using multi-valued adiabatic logic in 65 nm CMOS process. Microelectronics journal. pp. 26-34. [Online].