Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load. (August 2018) - Dubey, Avaneesh K.; Nagaria, R.K.
Abstract: A novel approach is proposed and discussed for designing CMOS double-tail dynamic comparator using the bulk-driven method. The bulk-driven method proposed thus far for low-power circuits result in reduced transconductance. The proposed technique uses the gate driven method to drive the inputs with bulk-driven loads. For the proposed comparator, mathematical analysis of delay and offset due to mismatch is presented. Additionally, a new optimized architecture of control unit is proposed to control both, offset voltage and kickback noise. To verify the outcomes, it is simulated in SPECTRE at 0.8 V of the supply voltage at 45 nm CMOS technology node. The proposed comparator achieves over 87% reduction in latch delay and 27% reduction of energy consumption over a conventional design. Monte-Carlo simulation is done to obtain the offset voltage, the result shows that the offset voltage is reduced by 62% using optimization technique. Highlights: This research article addresses two novel solutions for problem regarding double tail dynamic comparator. First is to improvement in latch speed by improving transconductance using bulk-driven load. And second is to design of an optimization technique to control offset voltage as well as kickback-noise.