A 10-bit 100-MS/s 5.23-mW SAR ADC in 0.18-μm CMOS. (August 2018)

• Record Type: Journal Article
• Authors: Ma, Rui; Wang, Lisha; Li, Dengquan; Ding, Ruixue; Zhu, Zhangming
• Is Part Of: Microelectronics journal. Volume 78(2018)
• Page Start: 63
• Page End: 72
• Publication Date: 2018-08
• Subjects: Analog-to-digital conversion -- SAR ADC -- Asynchronous -- CMOS -- Switching scheme; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2018.06.007
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: A 10-bit 100 MS/s energy-efficient successive-approximation analog-to-digital converter (SAR ADC) is presented in this paper. In order to improve the conversion rate and reduce power consumption as well, a modified spilt-capacitor VCM -based switching scheme is proposed. By utilizing the LSB capacitors to obtain the last-bit, the proposed switching scheme could decrease the area of capacitive DAC. Moreover, by modifying the switching behaviors of the most significant bit (MSB) and 2 nd -MSB, the conversion rate could be improved. The prototype SAR ADC fabricated in 0.18 μm CMOS achieves 53.68 dB SNDR and 62.85 dB SFDR at 100 MS/s sampling rate. The active area of the core is 0.216 mm 2 . It consumes 5.23 mW with 1.8 V supply, resulting in a Walden figure of merit (FoM) of 123.2 fJ/conversion step.