An ultra-low power output capacitor-less low-dropout regulator with slew-rate-enhanced circuit *Project supported by the National Natural Science Foundation of China (Nos. 61401137, 61404043, 61674049). (March 2018) - Cheng, Xin; Zhang, Yu; Xie, Guangjun; Yang, Yizhong; Zhang, Zhang
Abstract: An ultra-low power output-capacitorless low-dropout (LDO) regulator with a slew-rate-enhanced (SRE) circuit is introduced. The increased slew rate is achieved by sensing the transient output voltage of the LDO and then charging (or discharging) the gate capacitor quickly. In addition, a buffer with ultra-low output impedance is presented to improve line and load regulations. This design is fabricated by SMIC 0.18 μ m CMOS technology. Experimental results show that, the proposed LDO regulator only consumes an ultra-low quiescent current of 1.2 μ A. The output current range is from 10 μ A to 200 mA and the corresponding variation of output voltage is less than 40 mV. Moreover, the measured line regulation and load regulation are 15.38 mV/V and 0.4 mV/mA respectively.