10-bit segmented current steering DAC in 90nm CMOS technology. Issue 1 (April 2015)

• Record Type: Journal Article
• Authors: Bringas, R; Dy, F; Gerasta, O J
• Is Part Of: IOP conference series. Volume 79:Issue 1(2015)
• Publication Date: 2015-04
• Subjects: Materials science -- Periodicals; 620.1105
• DOI: 10.1088/1757-899X/79/1/012005
• Languages: English
• ISSNs: 1757-8981

Abstract

Abstract: This special project presents a 10-Bit 1Gs/s 1.2V/3.3V Digital-to-Analog Converter using1 Poly 9 Metal SAED 90-nm CMOS Technology intended for mixed-signal and power IC applications. To achieve maximum performance with minimum area, the DAC has been implemented in 6+4 Segmentation. The simulation results show a static performance of ±0.56 LSB INL and ±0.79 LSB DNL with a total layout chip area of 0.683 mm 2 .The segmented architecture is implemented using two sub DAC's, which are the LSB and MSB section with certain number bits. The DAC is designed using 4-BitBinary Weighted DAC for the LSB section and 6-BitThermometer-coded DAC for the MSB section. The thermometer-coded architecture provides the most optimized results in terms of linearity through reducing the clock feed-through effect especially in hot switching between multiple transistors. The binary- weighted architecture gives better linearity output in higher frequencies with better saturation in current sources.