Hole trapping in SiC-MOS devices evaluated by fast-capacitance–voltage method. (23rd March 2018)

• Record Type: Journal Article
• Authors: Hayashi, Mariko; Sometani, Mitsuru; Hatakeyama, Tetsuo; Yano, Hiroshi; Harada, Shinsuke
• Is Part Of: Japanese journal of applied physics. Volume 55:Number 4(2016:Apr.)Supplement 4
• Publication Date: 2018-03-23
• Subjects: Physics -- Periodicals; 621.05
• DOI: 10.7567/JJAP.57.04FR15
• Languages: English
• ISSNs: 0021-4922

Abstract

Abstract: We demonstrated a fast-capacitance–voltage (CV) method for the evaluation of the number and location of holes trapped in a 4H-SiC MOS device under negative gate bias stress. The number of trapped holes was carefully estimated by suppressing recombination and detrapping during stress relaxation. It was found that a large number of holes trapped in a short stress time were reduced by nitridation, and that the hole trapping in a long-stress-time region was accelerated by increases in temperature and electric field for a stress. From the results, we determined the respective model for hole trapping and detrapping.